1. Field of Invention
This invention relates to information processing systems, methods of operation and program products. More particularly, the invention relates to Processing Local Bus (PLB) architecture for multi-master and slave data transfers with overlapped read/write operations and scalable address pipelining: systems, methods and program products.
2. Description of Prior Art
Microprocessor based system central processing units and other bus masters require access to main memory locations. Main memory is typically distanced from the masters by at least one level of bridging between the masters and the memory bus. This bridging function is accomplished via a memory controller. The memory controller can be a sophisticated mechanism capable of accepting and ordering several different memory operations at any given moment in time. One of the problems associated with memory control is the initial memory latency inherent with dynamic random access memory, or DRAM. From the time that a master or CPU initiates a read request to main memory until the data is returned can be well over a dozen bus clock cycles. This latency negatively affects the overall system performance. To counteract the latency effect on reads to main memory the concept of xe2x80x9caddress pipeliningxe2x80x9d was introduced whereby the master would present a subsequent pending read request to the memory controller prior to completion of a preceding read operation. In this way the memory controller could better order and schedule use of the memory bus to decrease overall latency on subsequent pending reads. Also, other devices attached to the bus could claim operations destined for them in the future and allocate resources so that their initial latency is reduced. Further arbitration cycles, which use to operate sequentially with read and write transfers may now be performed in parallel with previous transfer requests in progress. What is needed in the art is a scalable address pipelining mechanism in a PLB architecture which can be used to programmably increase the depth of address pipelining independently on two overlapped read and write data buses while one operation is being performed and another operation is being performed at the same time.
Prior art related to address pipelining includes:
1. U.S. Pat. No. 6,081,860 entitled xe2x80x9cAddress Pipelining for Data Transfer,xe2x80x9d issued Jun. 27, 2000 filed Nov. 20, 1997 discloses a process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals, which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer. The design is configured to advantageously function in mixed systems, which may include address-pipelining and non-address-pipelining slave devices.
2. U.S. Pat. No. 4,626,843 entitled xe2x80x9cMulti-Master Communication Bus System with Parallel Bus Request Arbitrationxe2x80x9d issued Dec. 2, 1986 discloses apparatus and a related method for regulating access to a communication bus to which multiple communication nodes are connected. Control logic at each of the nodes determines which of them has priority to access the bus, by means of a parallel arbitration sequence in which all nodes contending for bus access participate. Specifically, each contending node generates a relative priority node number and asserts it onto an arbitration bus. All of the asserted node numbers are logically combined into a composite node number on the bus, and the winning node is determined in a bit-by-bit ripple comparison circuit at each node, the composite node number being compared with the locally generated relative priority node number. Priority is determined in advance of data transmission, and synchronization and arbitration take place without any central or master control unit.
3. U.S. Pat. No. 5,555,425 entitled xe2x80x9cMulti-Master Bus Arbitration System in Which the Address and Data Lines of the Bus May Be Separately Granted to Individual Masters,xe2x80x9d issued Sep. 10, 1996 discloses a multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master devices. Each master device is capable of originating a bus cycle to transmit data to or receive data from a desired slave device. The bus controller grants the bus to a selected master device, which enters an address master state and addresses the desired slave device. The selected master device is transferred to a bus master state where a data transfer to or from the slave device is initiated. The selected master device then transfers to a data master state unless the selected master device wants, and is permitted through an arbiter, to retain control of the bus. The bus controller grants a bus request to a requesting master device through to the arbiter. The requesting master device is transferred into the address master state while the selected master device is still in the data master state, thus performing a pipelining operation.
4. U.S. Pat. No. 5,640,527 entitled xe2x80x9cApparatus and Method for Address Pipelining of Dynamic Random Access Memory Utilizing Transparent Page Address Batches to Reduce Wait States,xe2x80x9d issued Jun. 17, 1997 discloses An apparatus and method for address pipelining of a computer system that reduce the average number of wait states required to access a dynamic random access memory (DRAM) subsystem. A memory controller addresses a plurality of random access memory integrated circuits in pages of addresses wherein contiguous address pages are in different ones of the plurality of dynamic random access memory integrated circuits. Transparent latches associated with each of the different ones of the plurality of dynamic random access memory integrated circuits allow pipelining of address setups for more than one memory page at substantially the same time. The apparatus and method improve the write access times of a computer system and, when used with a computer system having address pipelining, both read and write accesses are improved because address set up latency time is reduced.
5. U.S. Pat. No. 5,699,516 entitled xe2x80x9cMethod and Apparatus for Implementing In-Order Termination Bus Protocol Within a Data Processing System,xe2x80x9d issued Dec. 16, 1997 discloses a bus protocol is provided for pipelined and/or split transaction buses (18,48) which have in-order data bus termination and which do not require data bus arbitration. The present invention solves the problem of matching the initial address request by a bus master (12, 13, 42) to the corresponding data response from a bus slave (14, 15, 44) when the bus (18, 48) used for master-slave communication is a split-transaction bus and/or a pipelined bus. Each bus master (12, 13, 42) and each bus slave (14, 15, 44) has a counter (30-33, 75-76) which is used to store a current pipe depth value (21, 51) from a central pipe counter (16, 72). A transaction start signal (20, 50) and a transaction end signal (22, 52) are used to selectively increment and decrement the counters (30-33, 75-76).
6. U.S. Pat. No. 5,440,751 entitled xe2x80x9cBurst Data Transfer to Single Cycle Transfer Conversion and Stroke Single Conversion,xe2x80x9d issued Aug. 8, 1995 discloses an apparatus, which converts burst mode bus, cycles into single cycle mode cycles and converts separate address and data strobe signals into a single address strobe in a computer system. The apparatus also receives an address strobe signal, a number of address signals and the length of the burst when a device begins a burst cycle. After the first cycle of the burst transfer is complete, the apparatus initiates each subsequent cycle comprising the burst transfer by incrementing the address signals and providing additional address strobe signals until the burst is complete. The logic also facilitates address pipelining by monitoring a next address signal generated by the device. The apparatus monitors the separate address strobe and data strobe signals and generates the single address strobe signal on the next clock cycle after the address and data strobe signals are asserted. If only the address strobe signal is asserted at the beginning of a cycle, then the single address strobe signal is asserted only after valid data is available on the bus and the data strobe signal is asserted. The apparatus also monitors next address signals generated by the device to facilitate pipelining
7. U.S. Pat. No. 5,469,544 entitled xe2x80x9cCentral Processing Unit Address Pipelining,xe2x80x9d issued Nov. 21, 1995 discloses a microprocessor for use in a computer system which pipelines addresses for both burst and non-burst mode data transfers. By pipelining addresses, the microprocessor is able to increase the throughput of data transfers in the system. In the present invention, bits are used which may be programmed to disable and enable the address pipelining for the non-burst mode and burst mode transfers.
8. U.S. Pat. No. 5,553,248 entitled xe2x80x9cSystem for Awarding the Highest Priority to a Microprocessor Releasing a System Bus after Aborting A Locked Cycle upon Detecting A Locked Retry Signalxe2x80x9d issued Sep. 3, 1996 discloses three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)xc3x97(nxe2x88x921) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the nxe2x88x921 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISAI bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISAI bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.
None of the prior art discloses a multi-master computer system with overlapped read and write signal and scalable address pipelining to programmably increase the depth of address pipeling independently on two overlapped read and write data busses up to xe2x80x9cNxe2x80x9d deep request pipelining, the read and write pipeline depths being programmable to different values and providing information to masters of the highest priority request contained in both the read and write pipelines enabling the masters to determine the relative importance of pending transfer requests thereby permitting appropriate action during long burst transfers.
An object of the invention is an information processing system, method of operation and program product having scalable address pipeling which programmably increases the depth of address pipelining independently on overlapped read and write data busses of a multi-master computer system for reduced system latency.
Another object is a multi-master computer system, method, and program product providing information to masters of the highest priority request contained in both read and write pipelines of pending transfer requests.
Another object is a Processor Local Bus Architecture which provides programming of a number of addresses pipelined up to xe2x80x9cNxe2x80x9d deep requests where read and write pipeline depths may be programmed to different values.
These and other objects, features and advantages are achieved in a multi-master computer system, e.g. a Local Processing Bus (LPB) architecture for multi-Master and Slave data transfers with overlapped Read and Write operations and scalable address pipelining. The system includes a plurality of Master (CPU)devices and Slaves peripheral devices) connected to the LPB having address, read and write busses serviced by a PLB Arbiter. The Arbiter includes scalable Read Master pipeline logic for storing 0 to xe2x80x9cNxe2x80x9d read master identifications (Ids) corresponding to requests according to the order of the master bus grant; Read Slave pipeline logic for storing 0 to xe2x80x9cNxe2x80x9d Slave Ids acknowledging Read Master requests; Read priority pipeline logic for tracking master request priority involved in each pipe line transfer; scalable Write Master pipeline logic for storing O to xe2x80x9cNxe2x80x9d write Master (Ids) corresponding to requests and according to the order of the Master bus grant producing the highest priority in the pipeline request; Write Slave pipeline logic for storing 0 to xe2x80x9cNxe2x80x9d Slave Ids acknowledging Master Write requests, and Write Priority pipeline logic for tracking of Write request priority of Master devices according to the order of the bus grant producing the highest priority in the pipeline produce the highest priority of the Read or Write Master request to the bus or other Masters. A state machine controls the shifting of data transfer requests in the pipeline logic. To achieve scalable pipeline operation, the Arbiter samples each Slave Address Acknowledge (S1_addrAck) signal independently up to the number of Slaves supported. The Arbiter also provides a separate Read primary (PLB_rdPrim) and Write primary (PLB_wrPrim) signal to each Slave to notify the one and only one Slave positioned in the pipeline that has been promoted to the primary transfer. The means for broadcasting all pipeline transfers is via a Secondary Address Valid (PLB_SA Valid) signal. For a particular type of transfer, Read or Write, each subsequent assertion of the Secondary Address Valid signal by the Arbiter without an intervening assertion of a Primary Address Valid (PLB_PA Valid) signal is considered an increase in the depth of pipelining. A master receives an address acknowledge signal from the arbiter which routed the address acknowledge from the slave and awaits the appropriate data acknowledgement. A slave acknowledges a pipeline transfer without concern for its position in the pipeline. The master may request additional pipeline requests for the same bus as long as it continues to receive arbiter address acknowledgement assertions. The slave may or may not acknowledge subsequent assertions of the arbiter secondary address valid signal so as to claim as many pipeline transfers as possible. There is no bus timeout for a pipeline transfer for a slave which cannot acknowledge a secondary request in a reasonable amount of time. In such case the slave asserts a rearbitrate transfer (SL_rearbitrate) signal to allow the arbiter to advance to the next pending bus request. Separate read pending requests (PLB_rdPendReq) signals and write pending requests (PLB_wrPendReq) signals by the arbiter are available for sampling by the bus master. If a master request (Mn_request) is active or a secondary transfer has been acknowledged, the appropriate pending request signal is activated. Masters which perform long burst transfers sample the signal active upon their latency timer expiration and then the read or write bus request pending priority signals. The pending signals indicate the highest priority of all pending requests and all acknowledged transfers in the read pipeline. The write pending request priority signals the highest priority of all pending requests and also acknowledged transfers in the write pipeline queue. If a bursting master determines that a request of equal or higher priority is active or queued in the pipeline, the Master will terminate its data transfer and relinquish the bus.